168 lines
7.0 KiB
C++
168 lines
7.0 KiB
C++
/////////////////////////////////////////////////////////////////////
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// //
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// file: aUSBCSwitch.h //
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// //
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/////////////////////////////////////////////////////////////////////
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// //
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// description: USBCSwitch C++ Module object. //
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// //
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// build number: source //
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// //
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/////////////////////////////////////////////////////////////////////
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// //
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// Copyright (c) 2018 Acroname Inc. - All Rights Reserved //
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// //
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// This file is part of the BrainStem release. See the license.txt //
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// file included with this package or go to //
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// https://acroname.com/software/brainstem-development-kit //
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// for full license details. //
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/////////////////////////////////////////////////////////////////////
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#ifndef __aUSBCSwitch_H__
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#define __aUSBCSwitch_H__
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#include "BrainStem-all.h"
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#include "aProtocoldefs.h"
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/**
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* \defgroup aUSBCSwitch_Constants USBCSwitch Module Constants
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* @{
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*/
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#define aUSBCSWITCH_MODULE 6 /**< USBCSwitch module number */
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#define aUSBCSWITCH_NUM_STORES 2 /**< Number of Store instances available */
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#define aUSBCSWITCH_NUM_INTERNAL_SLOTS 12 /**< Store: Number of internal slots instances available */
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#define aUSBCSWITCH_NUM_RAM_SLOTS 1 /**< Store: Number of RAM slot instances available */
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#define aUSBCSWITCH_NUM_USB 1 /**< Number of USB instances available */
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#define aUSBCSWITCH_NUM_MUX 1 /**< Number of Mux instances available */
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#define aUSBCSWITCH_NUM_EQ 2 /**< Number of Equalizer instances available */
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#define aUSBCSWITCH_NUM_MUX_CHANNELS 4 /**< Number of Mux channels available */
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/** @} */
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/**
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* \defgroup aUSBCSwitch_Port_State_Defines Port State Definitions
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* \brief Bit defines for port state UInt32
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* \brief (Tip: Use _BIT(X) from aDefs.h to retrieve bit value)
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* @{
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*/
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// Example: if (state & _BIT(aUSBCSwitch_USB_VBUS_ENABLED))
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#define usbPortStateVBUS 0 /**< USB VBUS current state */
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#define usbPortStateUSB2A 1 /**< USB2 side A current state */
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#define usbPortStateUSB2B 2 /**< USB2 side B current state */
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#define usbPortStateSBU 3 /**< SBU current state */
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#define usbPortStateSS1 4 /**< SS1 current state */
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#define usbPortStateSS2 5 /**< SS2 A current state */
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#define usbPortStateCC1 6 /**< CC1 current state */
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#define usbPortStateCC2 7 /**< CC2 A current state */
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#define usbPortStateCCFlip 14 /**< CC flip status */
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#define usbPortStateSSFlip 15 /**< SS flip status */
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#define usbPortStateSBUFlip 16 /**< SBU flip status */
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#define usbPortStateUSB2Flip 17 /**< USB2 flip status */
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#define usbPortStateConnectionEstablished 23 /**< Connection established state */
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#define usbPortStateCC1Inject 26 /**< CC1 inject current state */
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#define usbPortStateCC2Inject 27 /**< CC2 inject current state */
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#define usbPortStateCC1Detect 28 /**< CC1 detect current state */
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#define usbPortStateCC2Detect 29 /**< CC2 detect current state */
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#define usbPortStateCC1LogicState 30 /**< CC1 logic current state */
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#define usbPortStateCC2LogicState 31 /**< CC2 logic current state */
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#define get_usbPortStateDaughterCard(var) ((var & (3 << 18)) >> 18) /**< Daughter card status */
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/** @} */
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#if defined(__cplusplus)
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/// \brief Concrete Module implementation of a USBCSwitch
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/// Allows a user to connect to and control an attached switch
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class aUSBCSwitch : public Acroname::BrainStem::Module
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{
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public:
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aUSBCSwitch(const uint8_t module = aUSBCSWITCH_MODULE,
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bool bAutoNetworking = true,
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const uint8_t model = aMODULE_TYPE_USBC_Switch) :
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Acroname::BrainStem::Module(module, bAutoNetworking, model)
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{
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store[storeInternalStore].init(this, storeInternalStore);
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store[storeRAMStore].init(this, storeRAMStore);
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system.init(this, 0);
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mux.init(this, 0);
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usb.init(this, 0);
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equalizer[equalizer2p0].init(this, equalizer2p0);
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equalizer[equalizer3p0].init(this, equalizer3p0);
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}
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Acroname::BrainStem::MuxClass mux; /**< Mux Class */
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Acroname::BrainStem::StoreClass store[aUSBCSWITCH_NUM_STORES]; /**< Store Class */
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Acroname::BrainStem::SystemClass system; /**< System Class *//**< Timer Class */
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Acroname::BrainStem::USBClass usb; /**< USB Class */
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Acroname::BrainStem::EqualizerClass equalizer[aUSBCSWITCH_NUM_EQ]; /**< Equalizer Class */
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/** Equalizer 3P0 transmitter configs */
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enum EQUALIZER_3P0_TRANSMITTER_CONFIGS {
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MUX_1db_COM_0db_900mV = 0,
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MUX_0db_COM_1db_900mV,
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MUX_1db_COM_1db_900mV,
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MUX_0db_COM_0db_900mV,
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MUX_0db_COM_0db_1100mV,
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MUX_1db_COM_0db_1100mV,
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MUX_0db_COM_1db_1100mV,
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MUX_2db_COM_2db_1100mV,
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MUX_0db_COM_0db_1300mV,
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};
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/** Equalizer 3P0 receiver configs */
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enum EQUALIZER_3P0_RECEIVER_CONFIGS {
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LEVEL_1_3P0 = 0,
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LEVEL_2_3P0,
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LEVEL_3_3P0,
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LEVEL_4_3P0,
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LEVEL_5_3P0,
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LEVEL_6_3P0,
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LEVEL_7_3P0,
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LEVEL_8_3P0,
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LEVEL_9_3P0,
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LEVEL_10_3P0,
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LEVEL_11_3P0,
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LEVEL_12_3P0,
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LEVEL_13_3P0,
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LEVEL_14_3P0,
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LEVEL_15_3P0,
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LEVEL_16_3P0,
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};
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/** Equalizer 2P0 transmitter configs */
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enum EQUALIZER_2P0_TRANSMITTER_CONFIGS {
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TRANSMITTER_2P0_40mV = 0,
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TRANSMITTER_2P0_60mV,
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TRANSMITTER_2P0_80mV,
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TRANSMITTER_2P0_0mV,
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};
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/** Equalizer 3P0 receiver configs */
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enum EQUALIZER_2P0_RECEIVER_CONFIGS {
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LEVEL_1_2P0 = 0,
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LEVEL_2_2P0,
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};
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/** Equalizer channels */
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enum EQUALIZER_CHANNELS {
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BOTH = 0,
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MUX,
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COMMON
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};
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/** Daughter Cards */
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enum daughtercard_type {
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NO_DAUGHTERCARD = 0,
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PASSIVE_DAUGHTERCARD,
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REDRIVER_DAUGHTERCARD,
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UNKNOWN_DAUGHTERCARD
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};
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};
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#endif//defined(__cplusplus)
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#endif /* aUSBCSwitch_h */
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