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drm/i915: Introduce i915_error_regs 

Introduce i915_error_regs as the EIR/EMR counterpart
to the IIR/IMR/IER i915_irq_regs, and update the irq
reset/postingstall to utilize them accordingly.

v2: Include xe compat versions

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250217070047.953-7-ville.syrjala@linux.intel.com
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Ville Syrjälä 2025-02-17 09:00:45 +02:00
parent d2093831ea
commit 474e1cd6fe
5 changed files with 65 additions and 2 deletions
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29
drivers/gpu/drm/i915/i915_irq.c
View File

@ -120,6 +120,29 @@ void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
intel_uncore_posting_read(uncore, regs.imr);
}
void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
{
intel_uncore_write(uncore, regs.emr, 0xffffffff);
intel_uncore_posting_read(uncore, regs.emr);
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
}
void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
u32 emr_val)
{
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_write(uncore, regs.emr, emr_val);
intel_uncore_posting_read(uncore, regs.emr);
}
/**
* ivb_parity_work - Workqueue called when a parity error interrupt
* occurred.
@ -867,6 +890,7 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv)
i9xx_display_irq_reset(dev_priv);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
dev_priv->irq_mask = ~0u;
}
@ -876,7 +900,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
struct intel_uncore *uncore = &dev_priv->uncore;
u32 enable_mask;
intel_uncore_write(uncore, EMR, i9xx_error_mask(dev_priv));
gen2_error_init(uncore, GEN2_ERROR_REGS, i9xx_error_mask(dev_priv));
dev_priv->irq_mask =
~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
@ -972,6 +996,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv)
i9xx_display_irq_reset(dev_priv);
gen2_error_reset(uncore, GEN2_ERROR_REGS);
gen2_irq_reset(uncore, GEN2_IRQ_REGS);
dev_priv->irq_mask = ~0u;
}
@ -1000,7 +1025,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
struct intel_uncore *uncore = &dev_priv->uncore;
u32 enable_mask;
intel_uncore_write(uncore, EMR, i965_error_mask(dev_priv));
gen2_error_init(uncore, GEN2_ERROR_REGS, i965_error_mask(dev_priv));
dev_priv->irq_mask =
~(I915_ASLE_INTERRUPT |

4
drivers/gpu/drm/i915/i915_irq.h
View File

@ -47,4 +47,8 @@ void gen2_irq_reset(struct intel_uncore *uncore, struct i915_irq_regs regs);
void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
u32 imr_val, u32 ier_val);
void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs);
void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
u32 emr_val);
#endif /* __I915_IRQ_H__ */

3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -472,6 +472,9 @@
#define GM45_ERROR_CP_PRIV (1 << 3)
#define I915_ERROR_MEMORY_REFRESH (1 << 1)
#define I915_ERROR_INSTRUCTION (1 << 0)
#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
#define INSTPM _MMIO(0x20c0)
#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts

8
drivers/gpu/drm/i915/i915_reg_defs.h
View File

@ -294,4 +294,12 @@ struct i915_irq_regs {
#define I915_IRQ_REGS(_imr, _ier, _iir) \
((const struct i915_irq_regs){ .imr = (_imr), .ier = (_ier), .iir = (_iir) })
struct i915_error_regs {
i915_reg_t emr;
i915_reg_t eir;
};
#define I915_ERROR_REGS(_emr, _eir) \
((const struct i915_error_regs){ .emr = (_emr), .eir = (_eir) })
#endif /* __I915_REG_DEFS__ */

23
drivers/gpu/drm/xe/display/ext/i915_irq.c
View File

@ -51,6 +51,29 @@ void gen2_irq_init(struct intel_uncore *uncore, struct i915_irq_regs regs,
intel_uncore_posting_read(uncore, regs.imr);
}
void gen2_error_reset(struct intel_uncore *uncore, struct i915_error_regs regs)
{
intel_uncore_write(uncore, regs.emr, 0xffffffff);
intel_uncore_posting_read(uncore, regs.emr);
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
}
void gen2_error_init(struct intel_uncore *uncore, struct i915_error_regs regs,
u32 emr_val)
{
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_write(uncore, regs.eir, 0xffffffff);
intel_uncore_posting_read(uncore, regs.eir);
intel_uncore_write(uncore, regs.emr, emr_val);
intel_uncore_posting_read(uncore, regs.emr);
}
bool intel_irqs_enabled(struct xe_device *xe)
{
return atomic_read(&xe->irq.enabled);