mfd: tps65219: Add support for TI TPS65215 PMIC
Use chip ID and chip_data struct to differentiate between devices in probe(). Add TPS65215 resource information. Update descriptions and copyright information to reflect the driver supports 2 PMIC devices. Signed-off-by: Shree Ramamoorthy <s-ramamoorthy@ti.com> Link: https://lore.kernel.org/r/20250206173725.386720-5-s-ramamoorthy@ti.com Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Shree Ramamoorthy
Lee Jones
parent
76b58d5111
commit
7f9ed27eea
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@ -1,8 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0
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//
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// Driver for TPS65219 Integrated Power Management Integrated Chips (PMIC)
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// Driver for TPS65215/TPS65219 Power Management Integrated Chips (PMIC)
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//
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// Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
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// Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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#include <linux/i2c.h>
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#include <linux/reboot.h>
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@ -59,6 +60,46 @@ static const struct resource tps65219_pwrbutton_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_PB_RISING_EDGE_DETECT, "rising"),
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};
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static const struct resource tps65215_regulator_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_SCG, "LDO1_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_OC, "LDO1_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO1_UV, "LDO1_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_SCG, "LDO2_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_OC, "LDO2_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_UV, "LDO2_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_SCG, "BUCK3_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_OC, "BUCK3_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_NEG_OC, "BUCK3_NEG_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_UV, "BUCK3_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_SCG, "BUCK1_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_OC, "BUCK1_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_NEG_OC, "BUCK1_NEG_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_UV, "BUCK1_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_SCG, "BUCK2_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_OC, "BUCK2_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_NEG_OC, "BUCK2_NEG_OC"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_UV, "BUCK2_UV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV, "BUCK1_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV, "BUCK2_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV, "BUCK3_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV, "LDO1_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_RV, "LDO2_RV"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK1_RV_SD, "BUCK1_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK2_RV_SD, "BUCK2_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_BUCK3_RV_SD, "BUCK3_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO1_RV_SD, "LDO1_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65215_INT_LDO2_RV_SD, "LDO2_RV_SD"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_TIMEOUT, "TIMEOUT"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_WARM, "SENSOR_3_WARM"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_WARM, "SENSOR_2_WARM"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_WARM, "SENSOR_1_WARM"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_WARM, "SENSOR_0_WARM"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_3_HOT, "SENSOR_3_HOT"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_2_HOT, "SENSOR_2_HOT"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_1_HOT, "SENSOR_1_HOT"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
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};
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static const struct resource tps65219_regulator_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_SCG, "LDO3_SCG"),
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_LDO3_OC, "LDO3_OC"),
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@ -109,6 +150,11 @@ static const struct resource tps65219_regulator_resources[] = {
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DEFINE_RES_IRQ_NAMED(TPS65219_INT_SENSOR_0_HOT, "SENSOR_0_HOT"),
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};
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static const struct mfd_cell tps65215_cells[] = {
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MFD_CELL_RES("tps65215-regulator", tps65215_regulator_resources),
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MFD_CELL_NAME("tps65215-gpio"),
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};
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static const struct mfd_cell tps65219_cells[] = {
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MFD_CELL_RES("tps65219-regulator", tps65219_regulator_resources),
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MFD_CELL_NAME("tps65219-gpio"),
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@ -136,6 +182,8 @@ static unsigned int bit3_offsets[] = { TPS65219_REG_INT_BUCK_1_2_POS }; /* Buck
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static unsigned int bit4_offsets[] = { TPS65219_REG_INT_BUCK_3_POS }; /* Buck 3 */
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static unsigned int bit5_offsets[] = { TPS65219_REG_INT_LDO_1_2_POS }; /* LDO 1-2 */
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static unsigned int bit6_offsets[] = { TPS65219_REG_INT_LDO_3_4_POS }; /* LDO 3-4 */
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static unsigned int tps65215_bit5_offsets[] = { TPS65215_REG_INT_LDO_1_POS };
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static unsigned int tps65215_bit6_offsets[] = { TPS65215_REG_INT_LDO_2_POS };
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static unsigned int bit7_offsets[] = { TPS65219_REG_INT_PB_POS }; /* Power Button */
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static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = {
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@ -149,9 +197,62 @@ static struct regmap_irq_sub_irq_map tps65219_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
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};
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static struct regmap_irq_sub_irq_map tps65215_sub_irq_offsets[] = {
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REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65215_bit5_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(tps65215_bit6_offsets),
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REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),
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};
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#define TPS65219_REGMAP_IRQ_REG(int_name, register_position) \
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REGMAP_IRQ_REG(int_name, register_position, int_name##_MASK)
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static const struct regmap_irq tps65215_irqs[] = {
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_SCG, TPS65215_REG_INT_LDO_1_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_OC, TPS65215_REG_INT_LDO_1_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO1_UV, TPS65215_REG_INT_LDO_1_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_SCG, TPS65215_REG_INT_LDO_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_OC, TPS65215_REG_INT_LDO_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_UV, TPS65215_REG_INT_LDO_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_SCG, TPS65219_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_OC, TPS65219_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_NEG_OC, TPS65219_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_UV, TPS65219_REG_INT_BUCK_3_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_SCG, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_OC, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_UV, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_SCG, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_OC, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_NEG_OC, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_UV, TPS65219_REG_INT_BUCK_1_2_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_WARM, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_WARM, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_WARM, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_WARM, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_3_HOT, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_2_HOT, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_1_HOT, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_SENSOR_0_HOT, TPS65219_REG_INT_SYS_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV, TPS65219_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV, TPS65219_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV, TPS65219_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV, TPS65219_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_RV, TPS65219_REG_INT_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK1_RV_SD, TPS65219_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK2_RV_SD, TPS65219_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_BUCK3_RV_SD, TPS65219_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO1_RV_SD, TPS65219_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65215_INT_LDO2_RV_SD, TPS65219_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_TIMEOUT, TPS65219_REG_INT_TO_RV_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_FALLING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
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};
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static const struct regmap_irq tps65219_irqs[] = {
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_SCG, TPS65219_REG_INT_LDO_3_4_POS),
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_LDO3_OC, TPS65219_REG_INT_LDO_3_4_POS),
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@ -204,6 +305,20 @@ static const struct regmap_irq tps65219_irqs[] = {
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TPS65219_REGMAP_IRQ_REG(TPS65219_INT_PB_RISING_EDGE_DETECT, TPS65219_REG_INT_PB_POS),
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};
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static const struct regmap_irq_chip tps65215_irq_chip = {
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.name = "tps65215_irq",
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.main_status = TPS65219_REG_INT_SOURCE,
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.num_main_regs = 1,
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.num_main_status_bits = 8,
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.irqs = tps65215_irqs,
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.num_irqs = ARRAY_SIZE(tps65215_irqs),
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.status_base = TPS65215_REG_INT_LDO_2,
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.ack_base = TPS65215_REG_INT_LDO_2,
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.clear_ack = 1,
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.num_regs = 8,
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.sub_reg_offsets = tps65215_sub_irq_offsets,
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};
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static const struct regmap_irq_chip tps65219_irq_chip = {
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.name = "tps65219_irq",
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.main_status = TPS65219_REG_INT_SOURCE,
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@ -218,9 +333,29 @@ static const struct regmap_irq_chip tps65219_irq_chip = {
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.sub_reg_offsets = tps65219_sub_irq_offsets,
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};
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struct tps65219_chip_data {
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const struct regmap_irq_chip *irq_chip;
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const struct mfd_cell *cells;
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int n_cells;
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};
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static struct tps65219_chip_data chip_info_table[] = {
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[TPS65215] = {
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.irq_chip = &tps65215_irq_chip,
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.cells = tps65215_cells,
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.n_cells = ARRAY_SIZE(tps65215_cells),
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},
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[TPS65219] = {
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.irq_chip = &tps65219_irq_chip,
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.cells = tps65219_cells,
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.n_cells = ARRAY_SIZE(tps65219_cells),
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},
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};
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static int tps65219_probe(struct i2c_client *client)
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{
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struct tps65219 *tps;
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struct tps65219_chip_data *pmic;
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bool pwr_button;
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int ret;
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@ -231,6 +366,8 @@ static int tps65219_probe(struct i2c_client *client)
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i2c_set_clientdata(client, tps);
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tps->dev = &client->dev;
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tps->chip_id = (uintptr_t)i2c_get_match_data(client);
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pmic = &chip_info_table[tps->chip_id];
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tps->regmap = devm_regmap_init_i2c(client, &tps65219_regmap_config);
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if (IS_ERR(tps->regmap)) {
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@ -239,14 +376,14 @@ static int tps65219_probe(struct i2c_client *client)
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return ret;
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}
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ret = devm_regmap_add_irq_chip(&client->dev, tps->regmap, client->irq,
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IRQF_ONESHOT, 0, &tps65219_irq_chip,
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ret = devm_regmap_add_irq_chip(tps->dev, tps->regmap, client->irq,
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IRQF_ONESHOT, 0, pmic->irq_chip,
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&tps->irq_data);
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if (ret)
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return ret;
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ret = devm_mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO,
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tps65219_cells, ARRAY_SIZE(tps65219_cells),
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pmic->cells, pmic->n_cells,
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NULL, 0, regmap_irq_get_domain(tps->irq_data));
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if (ret) {
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dev_err(tps->dev, "Failed to add child devices: %d\n", ret);
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@ -284,7 +421,8 @@ static int tps65219_probe(struct i2c_client *client)
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}
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static const struct of_device_id of_tps65219_match_table[] = {
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{ .compatible = "ti,tps65219", },
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{ .compatible = "ti,tps65215", .data = (void *)TPS65215, },
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{ .compatible = "ti,tps65219", .data = (void *)TPS65219, },
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{}
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};
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MODULE_DEVICE_TABLE(of, of_tps65219_match_table);
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@ -299,5 +437,5 @@ static struct i2c_driver tps65219_driver = {
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module_i2c_driver(tps65219_driver);
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MODULE_AUTHOR("Jerome Neanne <jneanne@baylibre.com>");
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MODULE_DESCRIPTION("TPS65219 power management IC driver");
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MODULE_DESCRIPTION("TPS65215/TPS65219 PMIC driver");
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MODULE_LICENSE("GPL");
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@ -1,8 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Functions to access TPS65219 Power Management IC.
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* Functions to access TPS65215/TPS65219 Power Management Integrated Chips
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*
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* Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/
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* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef MFD_TPS65219_H
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@ -13,8 +14,11 @@
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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/* TPS chip id list */
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#define TPS65219 0xF0
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/* Chip id list*/
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enum pmic_id {
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TPS65215,
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TPS65219,
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};
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/* I2C ID for TPS65219 part */
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#define TPS65219_I2C_ID 0x24
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@ -26,6 +30,7 @@
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#define TPS65219_REG_BUCKS_CONFIG 0x03
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#define TPS65219_REG_LDO4_VOUT 0x04
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#define TPS65219_REG_LDO3_VOUT 0x05
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#define TPS65215_REG_LDO2_VOUT 0x05
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#define TPS65219_REG_LDO2_VOUT 0x06
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#define TPS65219_REG_LDO1_VOUT 0x07
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#define TPS65219_REG_BUCK3_VOUT 0x8
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@ -33,6 +38,7 @@
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#define TPS65219_REG_BUCK1_VOUT 0xA
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#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB
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#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC
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#define TPS65215_REG_LDO2_SEQUENCE_SLOT 0xC
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||||
#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD
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||||
#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE
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||||
#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF
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||||
|
|
@ -67,9 +73,16 @@
|
|||
#define TPS65219_REG_DISCHARGE_CONFIG 0x2A
|
||||
/* main irq registers */
|
||||
#define TPS65219_REG_INT_SOURCE 0x2B
|
||||
/* 'sub irq' registers */
|
||||
|
||||
/* TPS65219 'sub irq' registers */
|
||||
#define TPS65219_REG_INT_LDO_3_4 0x2C
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||||
#define TPS65219_REG_INT_LDO_1_2 0x2D
|
||||
|
||||
/* TPS65215 specific 'sub irq' registers */
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||||
#define TPS65215_REG_INT_LDO_2 0x2C
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||||
#define TPS65215_REG_INT_LDO_1 0x2D
|
||||
|
||||
/* Common TPS65215 & TPS65219 'sub irq' registers */
|
||||
#define TPS65219_REG_INT_BUCK_3 0x2E
|
||||
#define TPS65219_REG_INT_BUCK_1_2 0x2F
|
||||
#define TPS65219_REG_INT_SYSTEM 0x30
|
||||
|
|
@ -86,6 +99,9 @@
|
|||
#define TPS65219_REG_INT_TO_RV_POS 6
|
||||
#define TPS65219_REG_INT_PB_POS 7
|
||||
|
||||
#define TPS65215_REG_INT_LDO_2_POS 0
|
||||
#define TPS65215_REG_INT_LDO_1_POS 1
|
||||
|
||||
#define TPS65219_REG_USER_NVM_CMD 0x34
|
||||
#define TPS65219_REG_POWER_UP_STATUS 0x35
|
||||
#define TPS65219_REG_SPARE_2 0x36
|
||||
|
|
@ -107,6 +123,7 @@
|
|||
#define TPS65219_ENABLE_LDO1_EN_MASK BIT(3)
|
||||
#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4)
|
||||
#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5)
|
||||
#define TPS65215_ENABLE_LDO2_EN_MASK BIT(5)
|
||||
#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6)
|
||||
/* power ON-OFF sequence slot */
|
||||
#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0)
|
||||
|
|
@ -172,6 +189,13 @@
|
|||
#define TPS65219_INT_LDO2_SCG_MASK BIT(3)
|
||||
#define TPS65219_INT_LDO2_OC_MASK BIT(4)
|
||||
#define TPS65219_INT_LDO2_UV_MASK BIT(5)
|
||||
/* TPS65215 LDO1-2*/
|
||||
#define TPS65215_INT_LDO1_SCG_MASK BIT(0)
|
||||
#define TPS65215_INT_LDO1_OC_MASK BIT(1)
|
||||
#define TPS65215_INT_LDO1_UV_MASK BIT(2)
|
||||
#define TPS65215_INT_LDO2_SCG_MASK BIT(0)
|
||||
#define TPS65215_INT_LDO2_OC_MASK BIT(1)
|
||||
#define TPS65215_INT_LDO2_UV_MASK BIT(2)
|
||||
/* BUCK3 */
|
||||
#define TPS65219_INT_BUCK3_SCG_MASK BIT(0)
|
||||
#define TPS65219_INT_BUCK3_OC_MASK BIT(1)
|
||||
|
|
@ -202,6 +226,7 @@
|
|||
#define TPS65219_INT_LDO1_RV_MASK BIT(3)
|
||||
#define TPS65219_INT_LDO2_RV_MASK BIT(4)
|
||||
#define TPS65219_INT_LDO3_RV_MASK BIT(5)
|
||||
#define TPS65215_INT_LDO2_RV_MASK BIT(5)
|
||||
#define TPS65219_INT_LDO4_RV_MASK BIT(6)
|
||||
/* Residual Voltage ShutDown */
|
||||
#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0)
|
||||
|
|
@ -210,6 +235,7 @@
|
|||
#define TPS65219_INT_LDO1_RV_SD_MASK BIT(3)
|
||||
#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4)
|
||||
#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5)
|
||||
#define TPS65215_INT_LDO2_RV_SD_MASK BIT(5)
|
||||
#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6)
|
||||
#define TPS65219_INT_TIMEOUT_MASK BIT(7)
|
||||
/* Power Button */
|
||||
|
|
@ -235,6 +261,14 @@ enum {
|
|||
TPS65219_INT_LDO4_SCG,
|
||||
TPS65219_INT_LDO4_OC,
|
||||
TPS65219_INT_LDO4_UV,
|
||||
/* TPS65215 LDO1*/
|
||||
TPS65215_INT_LDO1_SCG,
|
||||
TPS65215_INT_LDO1_OC,
|
||||
TPS65215_INT_LDO1_UV,
|
||||
/* TPS65215 LDO2*/
|
||||
TPS65215_INT_LDO2_SCG,
|
||||
TPS65215_INT_LDO2_OC,
|
||||
TPS65215_INT_LDO2_UV,
|
||||
/* LDO1-2 */
|
||||
TPS65219_INT_LDO1_SCG,
|
||||
TPS65219_INT_LDO1_OC,
|
||||
|
|
@ -271,6 +305,7 @@ enum {
|
|||
TPS65219_INT_BUCK3_RV,
|
||||
TPS65219_INT_LDO1_RV,
|
||||
TPS65219_INT_LDO2_RV,
|
||||
TPS65215_INT_LDO2_RV,
|
||||
TPS65219_INT_LDO3_RV,
|
||||
TPS65219_INT_LDO4_RV,
|
||||
/* Residual Voltage ShutDown */
|
||||
|
|
@ -278,6 +313,7 @@ enum {
|
|||
TPS65219_INT_BUCK2_RV_SD,
|
||||
TPS65219_INT_BUCK3_RV_SD,
|
||||
TPS65219_INT_LDO1_RV_SD,
|
||||
TPS65215_INT_LDO2_RV_SD,
|
||||
TPS65219_INT_LDO2_RV_SD,
|
||||
TPS65219_INT_LDO3_RV_SD,
|
||||
TPS65219_INT_LDO4_RV_SD,
|
||||
|
|
@ -287,6 +323,12 @@ enum {
|
|||
TPS65219_INT_PB_RISING_EDGE_DETECT,
|
||||
};
|
||||
|
||||
enum tps65215_regulator_id {
|
||||
/* DCDC's same as TPS65219 */
|
||||
/* LDO1 is the same as TPS65219 */
|
||||
TPS65215_LDO_2 = 4,
|
||||
};
|
||||
|
||||
enum tps65219_regulator_id {
|
||||
/* DCDC's */
|
||||
TPS65219_BUCK_1,
|
||||
|
|
@ -300,11 +342,26 @@ enum tps65219_regulator_id {
|
|||
};
|
||||
|
||||
/* Number of step-down converters available */
|
||||
#define TPS65219_NUM_DCDC 3
|
||||
#define TPS6521X_NUM_BUCKS 3
|
||||
/* Number of LDO voltage regulators available */
|
||||
#define TPS65219_NUM_LDO 4
|
||||
#define TPS65215_NUM_LDO 2
|
||||
/* Number of total regulators available */
|
||||
#define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO)
|
||||
#define TPS65219_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65219_NUM_LDO)
|
||||
#define TPS65215_NUM_REGULATOR (TPS6521X_NUM_BUCKS + TPS65215_NUM_LDO)
|
||||
|
||||
/* Define the TPS65215 IRQ numbers */
|
||||
enum tps65215_irqs {
|
||||
/* INT source registers */
|
||||
TPS65215_TO_RV_SD_SET_IRQ,
|
||||
TPS65215_RV_SET_IRQ,
|
||||
TPS65215_SYS_SET_IRQ,
|
||||
TPS65215_BUCK_1_2_SET_IRQ,
|
||||
TPS65215_BUCK_3_SET_IRQ,
|
||||
TPS65215_LDO_1_SET_IRQ,
|
||||
TPS65215_LDO_2_SET_IRQ,
|
||||
TPS65215_PB_SET_IRQ,
|
||||
};
|
||||
|
||||
/* Define the TPS65219 IRQ numbers */
|
||||
enum tps65219_irqs {
|
||||
|
|
@ -326,6 +383,7 @@ enum tps65219_irqs {
|
|||
*
|
||||
* @dev: MFD device
|
||||
* @regmap: Regmap for accessing the device registers
|
||||
* @chip_id: Chip ID
|
||||
* @irq_data: Regmap irq data used for the irq chip
|
||||
* @nb: notifier block for the restart handler
|
||||
*/
|
||||
|
|
@ -333,6 +391,7 @@ struct tps65219 {
|
|||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
|
||||
unsigned int chip_id;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct notifier_block nb;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue