soc: fixes for 6.18, part 4

A few last minute fixes came in this week:
 
  - interrupt and gpio numbers in foud separate i.MX8 specific
    devicetree files were wrong.
 
  - The vector length property in the C906 CPU description
    used the wrong unit.
 
  - Two bugs with uninitialized stack variables in the tee
    subsystem.
 
  - Alexander Stein now maintains additional devicetree files.
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Merge tag 'soc-fixes-6.18-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
 "A few last minute fixes came in this week:

   - interrupt and gpio numbers in foud separate i.MX8 specific
     devicetree files were wrong

   - The vector length property in the C906 CPU description used the
     wrong unit

   - Two bugs with uninitialized stack variables in the tee subsystem

   - Alexander Stein now maintains additional devicetree files"

* tag 'soc-fixes-6.18-4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  riscv: dts: allwinner: d1: fix vlenb property
  MAINTAINERS: Add entry for TQ-Systems AM335 device trees
  tee: qcomtee: initialize result before use in release worker
  arm64: dts: imx8qm-mek: fix mux-controller select/enable-gpios polarity
  tee: qcomtee: fix uninitialized pointers with free attribute
  ARM: dts: nxp: imx6ul: correct SAI3 interrupt line
  arm64: dts: imx8dxl-ss-conn: swap interrupts number of eqos
  arm64: dts: imx8dxl: Correct pcie-ep interrupt number
This commit is contained in:
Linus Torvalds 2025-11-28 09:57:31 -08:00
commit 7fa0d7744c
8 changed files with 15 additions and 8 deletions

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@ -26056,6 +26056,8 @@ S: Supported
W: https://www.tq-group.com/en/products/tq-embedded/ W: https://www.tq-group.com/en/products/tq-embedded/
F: arch/arm/boot/dts/nxp/imx/*mba*.dts* F: arch/arm/boot/dts/nxp/imx/*mba*.dts*
F: arch/arm/boot/dts/nxp/imx/*tqma*.dts* F: arch/arm/boot/dts/nxp/imx/*tqma*.dts*
F: arch/arm/boot/dts/ti/omap/*mba*.dts*
F: arch/arm/boot/dts/ti/omap/*tqma*.dts*
F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts* F: arch/arm64/boot/dts/freescale/fsl-*tqml*.dts*
F: arch/arm64/boot/dts/freescale/imx*mba*.dts* F: arch/arm64/boot/dts/freescale/imx*mba*.dts*
F: arch/arm64/boot/dts/freescale/imx*tqma*.dts* F: arch/arm64/boot/dts/freescale/imx*tqma*.dts*

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@ -339,7 +339,7 @@
#sound-dai-cells = <0>; #sound-dai-cells = <0>;
compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
reg = <0x02030000 0x4000>; reg = <0x02030000 0x4000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_SAI3_IPG>, clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
<&clks IMX6UL_CLK_SAI3>, <&clks IMX6UL_CLK_SAI3>,
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;

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@ -29,8 +29,8 @@
compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
reg = <0x5b050000 0x10000>; reg = <0x5b050000 0x10000>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq"; interrupt-names = "macirq", "eth_wake_irq";
clocks = <&eqos_lpcg IMX_LPCG_CLK_4>, clocks = <&eqos_lpcg IMX_LPCG_CLK_4>,
<&eqos_lpcg IMX_LPCG_CLK_6>, <&eqos_lpcg IMX_LPCG_CLK_6>,

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@ -54,3 +54,8 @@
interrupt-names = "dma"; interrupt-names = "dma";
}; };
}; };
&pcieb_ep {
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";
};

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@ -217,8 +217,8 @@
compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec_mux>; pinctrl-0 = <&pinctrl_typec_mux>;
select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_LOW>; select-gpios = <&lsio_gpio4 6 GPIO_ACTIVE_HIGH>;
enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; enable-gpios = <&lsio_gpio4 19 GPIO_ACTIVE_LOW>;
orientation-switch; orientation-switch;
port { port {

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@ -28,7 +28,7 @@
riscv,isa-base = "rv64i"; riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm", "xtheadvector"; "zifencei", "zihpm", "xtheadvector";
thead,vlenb = <128>; thead,vlenb = <16>;
#cooling-cells = <2>; #cooling-cells = <2>;
cpu0_intc: interrupt-controller { cpu0_intc: interrupt-controller {

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@ -645,7 +645,7 @@ static void qcomtee_get_version(struct tee_device *teedev,
static void qcomtee_get_qtee_feature_list(struct tee_context *ctx, u32 id, static void qcomtee_get_qtee_feature_list(struct tee_context *ctx, u32 id,
u32 *version) u32 *version)
{ {
struct qcomtee_object_invoke_ctx *oic __free(kfree); struct qcomtee_object_invoke_ctx *oic __free(kfree) = NULL;
struct qcomtee_object *client_env, *service; struct qcomtee_object *client_env, *service;
struct qcomtee_arg u[3] = { 0 }; struct qcomtee_arg u[3] = { 0 };
int result; int result;

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@ -82,7 +82,7 @@ static void qcomtee_do_release_qtee_object(struct work_struct *work)
{ {
struct qcomtee_object *object; struct qcomtee_object *object;
struct qcomtee *qcomtee; struct qcomtee *qcomtee;
int ret, result; int ret, result = 0;
/* RELEASE does not require any argument. */ /* RELEASE does not require any argument. */
struct qcomtee_arg args[] = { { .type = QCOMTEE_ARG_TYPE_INV } }; struct qcomtee_arg args[] = { { .type = QCOMTEE_ARG_TYPE_INV } };