phy: samsung-ufs: support ExynosAutov920 ufs phy driver
Add support for ExynosAutov920 ufs phy driver. Signed-off-by: Sowon Na <sowon.na@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20241226031142.1764652-3-sowon.na@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sowon Na
Vinod Koul
parent
0ee54dcfe7
commit
d231776772
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@ -7,6 +7,7 @@ phy-exynos-ufs-y += phy-gs101-ufs.o
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phy-exynos-ufs-y += phy-samsung-ufs.o
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phy-exynos-ufs-y += phy-exynos7-ufs.o
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phy-exynos-ufs-y += phy-exynosautov9-ufs.o
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phy-exynos-ufs-y += phy-exynosautov920-ufs.o
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phy-exynos-ufs-y += phy-fsd-ufs.o
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obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
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phy-exynos-usb2-y += phy-samsung-usb2.o
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@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* UFS PHY driver data for Samsung ExynosAuto v920 SoC
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*
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* Copyright (C) 2024 Samsung Electronics Co., Ltd.
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*/
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#include "phy-samsung-ufs.h"
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#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL 0x708
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#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
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#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
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#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
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#define EXYNOSAUTOV920_CDR_LOCK_OFFSET 0xce4
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#define PHY_EXYNOSAUTOV920_LANE_OFFSET 0x200
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#define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
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PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
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/* Calibration for phy initialization */
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static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
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PHY_COMN_REG_CFG(0x29, 0x22, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x3c, 0x14, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x04, 0x95, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x06, 0x30, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x200, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x201, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0c, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2e1, 0xc0, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x22d, 0xf8, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x234, 0x60, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x238, 0x13, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x239, 0x48, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x23a, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x23b, 0x29, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x23c, 0x2a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x23d, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x23e, 0x14, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x23f, 0x13, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4a, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x25d, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x25e, 0x3f, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x25f, 0xff, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x26f, 0xf0, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x273, 0x33, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x274, 0x50, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x284, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x285, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2a2, 0x04, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x27d, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2fa, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x286, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x287, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x288, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x289, 0x03, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2b3, 0x04, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2b6, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2b7, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2b8, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2b9, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2ba, 0x0b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2bb, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2bc, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2bd, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x2be, 0x06, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x34b, 0x01, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x34c, 0x24, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x34d, 0x23, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x34e, 0x45, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x34f, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x350, 0x31, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x351, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x352, 0x02, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x353, 0x00, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x354, 0x01, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
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END_UFS_PHY_CFG,
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};
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/* Calibration for HS mode series A/B */
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static const struct samsung_ufs_phy_cfg exynosautov920_pre_pwr_hs_cfg[] = {
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PHY_TRSV_REG_CFG_AUTOV920(0x369, 0x11, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x03, PWR_MODE_ANY),
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END_UFS_PHY_CFG,
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};
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static const struct samsung_ufs_phy_cfg exynosautov920_post_pwr_hs_cfg[] = {
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END_UFS_PHY_CFG,
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};
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#define DELAY_IN_US 40
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#define RETRY_CNT 100
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#define EXYNOSAUTOV920_CDR_LOCK_MASK 0x8
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int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane)
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{
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struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
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u32 reg, i;
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struct samsung_ufs_phy_cfg cfg[4] = {
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PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY),
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END_UFS_PHY_CFG,
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};
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for (i = 0; i < RETRY_CNT; i++) {
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udelay(DELAY_IN_US);
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reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CDR_LOCK_OFFSET +
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(PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) * lane));
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if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)
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== EXYNOSAUTOV920_CDR_LOCK_MASK) {
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samsung_ufs_phy_config(ufs_phy, &cfg[2], lane);
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return 0;
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}
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udelay(DELAY_IN_US);
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/* Disable and enable CDR */
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samsung_ufs_phy_config(ufs_phy, &cfg[0], lane);
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samsung_ufs_phy_config(ufs_phy, &cfg[1], lane);
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}
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dev_err(ufs_phy->dev, "failed to get phy cdr lock\n");
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return -ETIMEDOUT;
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}
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static const struct samsung_ufs_phy_cfg *exynosautov920_ufs_phy_cfgs[CFG_TAG_MAX] = {
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[CFG_PRE_INIT] = exynosautov920_pre_init_cfg,
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[CFG_PRE_PWR_HS] = exynosautov920_pre_pwr_hs_cfg,
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[CFG_POST_PWR_HS] = exynosautov920_post_pwr_hs_cfg,
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};
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static const char * const exynosautov920_ufs_phy_clks[] = {
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"ref_clk",
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};
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const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
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.cfgs = exynosautov920_ufs_phy_cfgs,
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.isol = {
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.offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL,
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.mask = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK,
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.en = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN,
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},
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.clk_list = exynosautov920_ufs_phy_clks,
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.num_clks = ARRAY_SIZE(exynosautov920_ufs_phy_clks),
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.cdr_lock_status_offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
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.wait_for_cdr = exynosautov920_ufs_phy_wait_cdr_lock,
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};
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@ -28,9 +28,9 @@
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#define PHY_DEF_LANE_CNT 1
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static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
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const struct samsung_ufs_phy_cfg *cfg,
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u8 lane)
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void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
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const struct samsung_ufs_phy_cfg *cfg,
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u8 lane)
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{
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enum {LANE_0, LANE_1}; /* lane index */
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@ -323,6 +323,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = {
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}, {
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.compatible = "samsung,exynosautov9-ufs-phy",
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.data = &exynosautov9_ufs_phy,
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}, {
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.compatible = "samsung,exynosautov920-ufs-phy",
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.data = &exynosautov920_ufs_phy,
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}, {
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.compatible = "tesla,fsd-ufs-phy",
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.data = &fsd_ufs_phy,
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@ -143,9 +143,13 @@ static inline void samsung_ufs_phy_ctrl_isol(
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}
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int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
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int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane);
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void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
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const struct samsung_ufs_phy_cfg *cfg, u8 lane);
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extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
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extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
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extern const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy;
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extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy;
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extern const struct samsung_ufs_phy_drvdata tensor_gs101_ufs_phy;
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