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Memory controller drivers for v6.18 

1. STM32 OMM: Fix ineffective/missing setting of the req2ack in the
    device based on DT property, if the value is different than 0.
 
 2. Samsung Exynos SROM: Fix IO map resource leak if
    of_platform_populate() in probe() failed.
 
 3. Broadcom brcmstb: Document existing, older devices in Devicetree
    bindings.
 
 4. Tegra 210 EMC: Document OPP table for interconnects (driver usage
    will come later) and define memory client IDs as bindings, because
    these are shared between DTS and driver.
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Merge tag 'memory-controller-drv-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.18

1. STM32 OMM: Fix ineffective/missing setting of the req2ack in the
   device based on DT property, if the value is different than 0.

2. Samsung Exynos SROM: Fix IO map resource leak if
   of_platform_populate() in probe() failed.

3. Broadcom brcmstb: Document existing, older devices in Devicetree
   bindings.

4. Tegra 210 EMC: Document OPP table for interconnects (driver usage
   will come later) and define memory client IDs as bindings, because
   these are shared between DTS and driver.

* tag 'memory-controller-drv-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra210: Use bindings for client ids
  dt-bindings: memory: tegra210: Add memory client IDs
  dt-bindings: memory: tegra210: emc: Document OPP table and interconnect
  dt-bindings: memory: Update brcmstb-memc-ddr binding with older chips
  memory: samsung: exynos-srom: Fix of_iomap leak in exynos_srom_probe
  memory: stm32_omm: Fix req2ack update test

Link: https://lore.kernel.org/r/20250912140030.204650-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-23 23:07:31 +02:00
parent 7150189b62 3804cef4c5
commit ebc5eb9ea0
6 changed files with 167 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml
View File

@ -42,6 +42,10 @@ properties:
items:
- const: brcm,brcmstb-memc-ddr-rev-b.1.x
- const: brcm,brcmstb-memc-ddr
- description: Revision 0.x controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-a.0.0
- const: brcm,brcmstb-memc-ddr
reg:
maxItems: 1

11
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
View File

@ -33,6 +33,9 @@ properties:
items:
- description: EMC general interrupt
"#interconnect-cells":
const: 0
memory-region:
maxItems: 1
description:
@ -44,6 +47,11 @@ properties:
description:
phandle of the memory controller node
operating-points-v2:
description:
Should contain freqs and voltages and opp-supported-hw property, which
is a bitfield indicating SoC speedo ID mask.
required:
- compatible
- reg
@ -79,4 +87,7 @@ examples:
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&emc_table>;
nvidia,memory-controller = <&mc>;
operating-points-v2 = <&dvfs_opp_table>;
#interconnect-cells = <0>;
};

10
drivers/memory/samsung/exynos-srom.c
View File

@ -121,20 +121,18 @@ static int exynos_srom_probe(struct platform_device *pdev)
return -ENOMEM;
srom->dev = dev;
srom->reg_base = of_iomap(np, 0);
if (!srom->reg_base) {
srom->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(srom->reg_base)) {
dev_err(&pdev->dev, "iomap of exynos srom controller failed\n");
return -ENOMEM;
return PTR_ERR(srom->reg_base);
}
platform_set_drvdata(pdev, srom);
srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
ARRAY_SIZE(exynos_srom_offsets));
if (!srom->reg_offset) {
iounmap(srom->reg_base);
if (!srom->reg_offset)
return -ENOMEM;
}
for_each_child_of_node(np, child) {
if (exynos_srom_configure_bank(srom, child)) {

2
drivers/memory/stm32_omm.c
View File

@ -238,7 +238,7 @@ static int stm32_omm_configure(struct device *dev)
if (mux & CR_MUXEN) {
ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns",
&req2ack);
if (!ret && !req2ack) {
if (!ret && req2ack) {
req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1;
if (req2ack > 256)

146
drivers/memory/tegra/tegra210.c
View File

@ -9,11 +9,11 @@
static const struct tegra_mc_client tegra210_mc_clients[] = {
{
.id = 0x00,
.id = TEGRA210_MC_PTCR,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
}, {
.id = 0x01,
.id = TEGRA210_MC_DISPLAY0A,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
@ -29,7 +29,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x02,
.id = TEGRA210_MC_DISPLAY0AB,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
@ -45,7 +45,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x03,
.id = TEGRA210_MC_DISPLAY0B,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
@ -61,7 +61,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x04,
.id = TEGRA210_MC_DISPLAY0BB,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
@ -77,7 +77,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x05,
.id = TEGRA210_MC_DISPLAY0C,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
@ -93,7 +93,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x06,
.id = TEGRA210_MC_DISPLAY0CB,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
@ -109,7 +109,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x0e,
.id = TEGRA210_MC_AFIR,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
@ -125,7 +125,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x0f,
.id = TEGRA210_MC_AVPCARM7R,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
@ -141,7 +141,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x10,
.id = TEGRA210_MC_DISPLAYHC,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
@ -157,7 +157,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x11,
.id = TEGRA210_MC_DISPLAYHCB,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
.regs = {
@ -173,7 +173,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x15,
.id = TEGRA210_MC_HDAR,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
@ -189,7 +189,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x16,
.id = TEGRA210_MC_HOST1XDMAR,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
@ -205,7 +205,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x17,
.id = TEGRA210_MC_HOST1XR,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
@ -221,7 +221,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x1c,
.id = TEGRA210_MC_NVENCSRD,
.name = "nvencsrd",
.swgroup = TEGRA_SWGROUP_NVENC,
.regs = {
@ -237,7 +237,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x1d,
.id = TEGRA210_MC_PPCSAHBDMAR,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
@ -253,7 +253,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x1e,
.id = TEGRA210_MC_PPCSAHBSLVR,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
@ -269,7 +269,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x1f,
.id = TEGRA210_MC_SATAR,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
@ -285,7 +285,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x27,
.id = TEGRA210_MC_MPCORER,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
@ -297,7 +297,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x2b,
.id = TEGRA210_MC_NVENCSWR,
.name = "nvencswr",
.swgroup = TEGRA_SWGROUP_NVENC,
.regs = {
@ -313,7 +313,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x31,
.id = TEGRA210_MC_AFIW,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
.regs = {
@ -329,7 +329,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x32,
.id = TEGRA210_MC_AVPCARM7W,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
.regs = {
@ -345,7 +345,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x35,
.id = TEGRA210_MC_HDAW,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
.regs = {
@ -361,7 +361,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x36,
.id = TEGRA210_MC_HOST1XW,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
.regs = {
@ -377,7 +377,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x39,
.id = TEGRA210_MC_MPCOREW,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
.regs = {
@ -389,7 +389,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x3b,
.id = TEGRA210_MC_PPCSAHBDMAW,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
@ -405,7 +405,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x3c,
.id = TEGRA210_MC_PPCSAHBSLVW,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
.regs = {
@ -421,7 +421,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x3d,
.id = TEGRA210_MC_SATAW,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
.regs = {
@ -437,7 +437,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x44,
.id = TEGRA210_MC_ISPRA,
.name = "ispra",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
@ -453,7 +453,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x46,
.id = TEGRA210_MC_ISPWA,
.name = "ispwa",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
@ -469,7 +469,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x47,
.id = TEGRA210_MC_ISPWB,
.name = "ispwb",
.swgroup = TEGRA_SWGROUP_ISP2,
.regs = {
@ -485,7 +485,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x4a,
.id = TEGRA210_MC_XUSB_HOSTR,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
@ -501,7 +501,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x4b,
.id = TEGRA210_MC_XUSB_HOSTW,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
.regs = {
@ -517,7 +517,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x4c,
.id = TEGRA210_MC_XUSB_DEVR,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
@ -533,7 +533,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x4d,
.id = TEGRA210_MC_XUSB_DEVW,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
.regs = {
@ -549,7 +549,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x4e,
.id = TEGRA210_MC_ISPRAB,
.name = "isprab",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
@ -565,7 +565,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x50,
.id = TEGRA210_MC_ISPWAB,
.name = "ispwab",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
@ -581,7 +581,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x51,
.id = TEGRA210_MC_ISPWBB,
.name = "ispwbb",
.swgroup = TEGRA_SWGROUP_ISP2B,
.regs = {
@ -597,7 +597,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x54,
.id = TEGRA210_MC_TSECSRD,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
@ -613,7 +613,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x55,
.id = TEGRA210_MC_TSECSWR,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
.regs = {
@ -629,7 +629,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x56,
.id = TEGRA210_MC_A9AVPSCR,
.name = "a9avpscr",
.swgroup = TEGRA_SWGROUP_A9AVP,
.regs = {
@ -645,7 +645,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x57,
.id = TEGRA210_MC_A9AVPSCW,
.name = "a9avpscw",
.swgroup = TEGRA_SWGROUP_A9AVP,
.regs = {
@ -661,7 +661,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x58,
.id = TEGRA210_MC_GPUSRD,
.name = "gpusrd",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
@ -678,7 +678,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x59,
.id = TEGRA210_MC_GPUSWR,
.name = "gpuswr",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
@ -695,7 +695,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x5a,
.id = TEGRA210_MC_DISPLAYT,
.name = "displayt",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
@ -711,7 +711,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x60,
.id = TEGRA210_MC_SDMMCRA,
.name = "sdmmcra",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
.regs = {
@ -727,7 +727,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x61,
.id = TEGRA210_MC_SDMMCRAA,
.name = "sdmmcraa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
.regs = {
@ -743,7 +743,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x62,
.id = TEGRA210_MC_SDMMCR,
.name = "sdmmcr",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
.regs = {
@ -759,7 +759,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x63,
.id = TEGRA210_MC_SDMMCRAB,
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.name = "sdmmcrab",
.regs = {
@ -775,7 +775,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x64,
.id = TEGRA210_MC_SDMMCWA,
.name = "sdmmcwa",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
.regs = {
@ -791,7 +791,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x65,
.id = TEGRA210_MC_SDMMCWAA,
.name = "sdmmcwaa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
.regs = {
@ -807,7 +807,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x66,
.id = TEGRA210_MC_SDMMCW,
.name = "sdmmcw",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
.regs = {
@ -823,7 +823,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x67,
.id = TEGRA210_MC_SDMMCWAB,
.name = "sdmmcwab",
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.regs = {
@ -839,7 +839,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x6c,
.id = TEGRA210_MC_VICSRD,
.name = "vicsrd",
.swgroup = TEGRA_SWGROUP_VIC,
.regs = {
@ -855,7 +855,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x6d,
.id = TEGRA210_MC_VICSWR,
.name = "vicswr",
.swgroup = TEGRA_SWGROUP_VIC,
.regs = {
@ -871,7 +871,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x72,
.id = TEGRA210_MC_VIW,
.name = "viw",
.swgroup = TEGRA_SWGROUP_VI,
.regs = {
@ -887,7 +887,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x73,
.id = TEGRA210_MC_DISPLAYD,
.name = "displayd",
.swgroup = TEGRA_SWGROUP_DC,
.regs = {
@ -903,7 +903,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x78,
.id = TEGRA210_MC_NVDECSRD,
.name = "nvdecsrd",
.swgroup = TEGRA_SWGROUP_NVDEC,
.regs = {
@ -919,7 +919,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x79,
.id = TEGRA210_MC_NVDECSWR,
.name = "nvdecswr",
.swgroup = TEGRA_SWGROUP_NVDEC,
.regs = {
@ -935,7 +935,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x7a,
.id = TEGRA210_MC_APER,
.name = "aper",
.swgroup = TEGRA_SWGROUP_APE,
.regs = {
@ -951,7 +951,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x7b,
.id = TEGRA210_MC_APEW,
.name = "apew",
.swgroup = TEGRA_SWGROUP_APE,
.regs = {
@ -967,7 +967,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x7e,
.id = TEGRA210_MC_NVJPGRD,
.name = "nvjpgsrd",
.swgroup = TEGRA_SWGROUP_NVJPG,
.regs = {
@ -983,7 +983,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x7f,
.id = TEGRA210_MC_NVJPGWR,
.name = "nvjpgswr",
.swgroup = TEGRA_SWGROUP_NVJPG,
.regs = {
@ -999,7 +999,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x80,
.id = TEGRA210_MC_SESRD,
.name = "sesrd",
.swgroup = TEGRA_SWGROUP_SE,
.regs = {
@ -1015,7 +1015,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x81,
.id = TEGRA210_MC_SESRD,
.name = "seswr",
.swgroup = TEGRA_SWGROUP_SE,
.regs = {
@ -1031,7 +1031,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x82,
.id = TEGRA210_MC_AXIAPR,
.name = "axiapr",
.swgroup = TEGRA_SWGROUP_AXIAP,
.regs = {
@ -1047,7 +1047,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x83,
.id = TEGRA210_MC_AXIAPW,
.name = "axiapw",
.swgroup = TEGRA_SWGROUP_AXIAP,
.regs = {
@ -1063,7 +1063,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x84,
.id = TEGRA210_MC_ETRR,
.name = "etrr",
.swgroup = TEGRA_SWGROUP_ETR,
.regs = {
@ -1079,7 +1079,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x85,
.id = TEGRA210_MC_ETRR,
.name = "etrw",
.swgroup = TEGRA_SWGROUP_ETR,
.regs = {
@ -1095,7 +1095,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x86,
.id = TEGRA210_MC_TSECSRDB,
.name = "tsecsrdb",
.swgroup = TEGRA_SWGROUP_TSECB,
.regs = {
@ -1111,7 +1111,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x87,
.id = TEGRA210_MC_TSECSWRB,
.name = "tsecswrb",
.swgroup = TEGRA_SWGROUP_TSECB,
.regs = {
@ -1127,7 +1127,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x88,
.id = TEGRA210_MC_GPUSRD2,
.name = "gpusrd2",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {
@ -1144,7 +1144,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
},
},
}, {
.id = 0x89,
.id = TEGRA210_MC_GPUSWR2,
.name = "gpuswr2",
.swgroup = TEGRA_SWGROUP_GPU,
.regs = {

74
include/dt-bindings/memory/tegra210-mc.h
View File

@ -75,4 +75,78 @@
#define TEGRA210_MC_RESET_ETR 28
#define TEGRA210_MC_RESET_TSECB 29
#define TEGRA210_MC_PTCR 0
#define TEGRA210_MC_DISPLAY0A 1
#define TEGRA210_MC_DISPLAY0AB 2
#define TEGRA210_MC_DISPLAY0B 3
#define TEGRA210_MC_DISPLAY0BB 4
#define TEGRA210_MC_DISPLAY0C 5
#define TEGRA210_MC_DISPLAY0CB 6
#define TEGRA210_MC_AFIR 14
#define TEGRA210_MC_AVPCARM7R 15
#define TEGRA210_MC_DISPLAYHC 16
#define TEGRA210_MC_DISPLAYHCB 17
#define TEGRA210_MC_HDAR 21
#define TEGRA210_MC_HOST1XDMAR 22
#define TEGRA210_MC_HOST1XR 23
#define TEGRA210_MC_NVENCSRD 28
#define TEGRA210_MC_PPCSAHBDMAR 29
#define TEGRA210_MC_PPCSAHBSLVR 30
#define TEGRA210_MC_SATAR 31
#define TEGRA210_MC_MPCORER 39
#define TEGRA210_MC_NVENCSWR 43
#define TEGRA210_MC_AFIW 49
#define TEGRA210_MC_AVPCARM7W 50
#define TEGRA210_MC_HDAW 53
#define TEGRA210_MC_HOST1XW 54
#define TEGRA210_MC_MPCOREW 57
#define TEGRA210_MC_PPCSAHBDMAW 59
#define TEGRA210_MC_PPCSAHBSLVW 60
#define TEGRA210_MC_SATAW 61
#define TEGRA210_MC_ISPRA 68
#define TEGRA210_MC_ISPWA 70
#define TEGRA210_MC_ISPWB 71
#define TEGRA210_MC_XUSB_HOSTR 74
#define TEGRA210_MC_XUSB_HOSTW 75
#define TEGRA210_MC_XUSB_DEVR 76
#define TEGRA210_MC_XUSB_DEVW 77
#define TEGRA210_MC_ISPRAB 78
#define TEGRA210_MC_ISPWAB 80
#define TEGRA210_MC_ISPWBB 81
#define TEGRA210_MC_TSECSRD 84
#define TEGRA210_MC_TSECSWR 85
#define TEGRA210_MC_A9AVPSCR 86
#define TEGRA210_MC_A9AVPSCW 87
#define TEGRA210_MC_GPUSRD 88
#define TEGRA210_MC_GPUSWR 89
#define TEGRA210_MC_DISPLAYT 90
#define TEGRA210_MC_SDMMCRA 96
#define TEGRA210_MC_SDMMCRAA 97
#define TEGRA210_MC_SDMMCR 98
#define TEGRA210_MC_SDMMCRAB 99
#define TEGRA210_MC_SDMMCWA 100
#define TEGRA210_MC_SDMMCWAA 101
#define TEGRA210_MC_SDMMCW 102
#define TEGRA210_MC_SDMMCWAB 103
#define TEGRA210_MC_VICSRD 108
#define TEGRA210_MC_VICSWR 109
#define TEGRA210_MC_VIW 114
#define TEGRA210_MC_DISPLAYD 115
#define TEGRA210_MC_NVDECSRD 120
#define TEGRA210_MC_NVDECSWR 121
#define TEGRA210_MC_APER 122
#define TEGRA210_MC_APEW 123
#define TEGRA210_MC_NVJPGRD 126
#define TEGRA210_MC_NVJPGWR 127
#define TEGRA210_MC_SESRD 128
#define TEGRA210_MC_SESWR 129
#define TEGRA210_MC_AXIAPR 130
#define TEGRA210_MC_AXIAPW 131
#define TEGRA210_MC_ETRR 132
#define TEGRA210_MC_ETRW 133
#define TEGRA210_MC_TSECSRDB 134
#define TEGRA210_MC_TSECSWRB 135
#define TEGRA210_MC_GPUSRD2 136
#define TEGRA210_MC_GPUSWR2 137
#endif