umber-kernel/drivers/gpu/drm/xe/instructions
Tvrtko Ursulin e8372edec9 drm/xe/xelp: Implement Wa_16010904313
Add XeLP workaround 16010904313.

The description calls for it to be emitted as the indirect context buffer
workaround for render and compute, and from the workaround batch buffer
for the other engines. Therefore we plug into the previously added
respective top level emission functions.

The actual command streamer programming sequence differs from what is
described in the PRM, in that it assumes the listed LRCA offset was
supposed to actually refer to the location of the CTX_TIMESTAMP register
instead of LRCA + 0x180c (which is in GPR space). Latter appears to make
more sense under the assumption that multiple writes are helping with
restoring the CTX_TIMESTAMP register content from the saved context state.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20250711160153.49833-8-tvrtko.ursulin@igalia.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-07-25 08:42:49 -07:00
..
xe_alu_commands.h drm/xe: Add MI_MATH and ALU instruction definitions 2025-03-12 11:37:50 +01:00
xe_gfx_state_commands.h
xe_gfxpipe_commands.h drm/xe/xe3: Recognize 3DSTATE_COARSE_PIXEL in LRC dumps 2025-03-10 10:23:12 -07:00
xe_gpu_commands.h drm/xe: Invalidate L3 read-only cachelines for geometry streams too 2025-03-31 12:18:41 -04:00
xe_gsc_commands.h
xe_instr_defs.h drm/xe/pxp: Add VCS inline termination support 2025-02-03 11:51:09 -08:00
xe_mfx_commands.h drm/xe/pxp: Add VCS inline termination support 2025-02-03 11:51:09 -08:00
xe_mi_commands.h drm/xe/xelp: Implement Wa_16010904313 2025-07-25 08:42:49 -07:00